Crucial X6
SSD Specification and Info
Crucial X6 is an Entry-Level SATA SSD produced and sold by Crucial. The device comes with USB 3.2 Gen 2x1 interface and M.2 form factor - a good fit for both desktop and laptop computers. This SSD has a maximum sequential read-write speed of up to 540 MB per second, making it ideal for gaming and workstation PCs.
Due to its lack of DRAM memory, Crucial X6 has slight disadvantages over SSDs with DRAM memory. This SSD is using a Q:C NAND flash memory with 96 cell layers.
NAND type
The Controller
Crucial X6 is using SMI SM2259XT SSD controller to connect the NAND memory to the USB 3.2 Gen 2x1 interface. The controller has Single-core, 4-ch, 4-CE/ch configuration.
Typically, SSD controllers are microprocessors. In this case we have Single-core, 4-ch, 4-CE/ch processor responsible for controlling the SSD in such way, so that the data coming from the interface can be stored on to the NAND flash memory.
Some SSDs have simpler controllers with fewer communication channels and less cores.
Among other things, the controller also manages the SLC caching, optimizing the DRAM cache, encryption, LDPC, garbage collection, wear-leveling as well as TRIM
DRAM Cache
Crucial X6 has no separate DRAM chip to store the SD mapping tables to speeds up the data access.
As soon as the OS requests some data from the SSD, the SSD needs to know exactly where it is on the drive. Because garbage collection moves the data constantly, the controller relies on the mapping tables to locate it.
These tables are stored in DRAM cache, where they are accessed much more quickly than in NAND flash.
Therefore, SSDs with DRAM-less architecture have more random write and read operations. This makes the device perform worse and last shorter if they are not HMB enabled.
HMB Support
There is no HMB architecture available on the Crucial X6 to store the mapping tables. The device either doesn't support the architecture or uses DRAM cache.
The HBM is used to reduce the cost of production of NVMe SSDs with DRAM Cache, SSDs with this type of controllers can leverages the host system's DRAM instead of an onboard DRAM chip to host the FTL mapping table used by flash storage.